I. Field of the Invention
The present invention generally relates to the testing of electronic circuit boards and, more particularly, to board test fixtures and methods thereof for electrically interconnecting electronic circuit boards and the like to electrical test systems.
II. Related Art
A board test system consists of numerous electronic drivers (sources) and receivers (detectors) which are connected through an electronic switching mechanism, often referred to as a "scanner", to a plurality of contact points referred to as scanner pins. A board test fixture then provides an interface between these scanner pins and the electronic components located on an electronic circuit board. Because the electronic test signals which are used to determine whether the electronic component is operating properly must pass through the board test fixture both on their way to and from the electronic component, the board test fixture must maintain the signal quality of the test signals to ensure that the electronic component is not incorrectly diagnosed as operating either properly or improperly.
It has been recognized in the art that in order to ensure maximum test signal quality, the length of the signal path between the scanner and the electronic circuit board must be kept as short as possible. This factor normally dictates a short vertical coupling of the test system and the circuit board. In other words, a "short-wire" board test fixture is designed to sit directly on top of the scanner and the electronic circuit board directly on the board test fixture. Furthermore, any board test fixture must be easy to assemble and maintain in order to be readily usable and cost effective. Finally, the ability to automate the assembly of the fixture is also an important feature.
U.S. Pat. No. 4,799,007 to Cook et al., which is incorporated herein by reference, describes a board test fixture which provides short and reliable connections between a test system and a circuit board under test. The foregoing short-wire fixture provides for good signal fidelity with digital signals up to approximately 6 megahertz (MHz). However, due to electrical parasitics, signal fidelity begins to fall off above about 6 MHz, and the ability to accurately test can become difficult above around 12 MHz.
The electrical parasitics phenomenon is discussed with reference to FIG. 1. Electrical parasitics become apparent in the form of a phenomenum known in the art as "ground bounce" or voltage/current "spikes". Ground bounce is often caused by the quick transitioning of the outputs of the circuit board under test. As shown in FIG. 1 at reference 102, the various outputs of the circuit board under test are connected to the receivers of the test system via the board test fixture. Furthermore, as shown at reference 104, the inputs of the board under test are connected to driver outputs of the test system via the board test fixture. The board test fixture comprises wiring which is schematically shown in FIG. 1 as inductances L.sub.r, L.sub.g, L.sub.d.
Now, in operation, when a circuit board output 106 switches, the receiver input current I.sub.r must pass through the fixture wiring to charge the input capacitance C.sub.r of the receiver 108. The capacitance C.sub.r comprises the actual receiver input capacitance in combination with the board trace capacitance. The magnitude of the charging current I.sub.r can be predicted from the following formula: I.sub.r =C.sub.r * (dV.sub.r /dt). Because the capacitance C.sub.r is largely fixed in the board test system, the primary determining factor in the magnitude of the current I.sub.r is the switching speed of the board output.
The current I.sub.r which flows from the board output to the test system must in some way return to the circuit board under test by some electrical path in order to satisfy Kirchoff's current laws. While a small part of the current I.sub.r may be returned by other paths, the majority of it will flow through the fixture ground wires, as indicated by reference 110 as a current I.sub.g.
The ground current I.sub.g flowing through the fixture ground wiring will induce a voltage V.sub.g across the wire inductance L.sub.g, wherein V.sub.g =L.sub.g * (dI.sub.g /dt). As indicated by the foregoing equation, the switching speed of the circuit board under test affects the voltage V.sub.g across the wire inductance L.sub.g. In other words, the induced voltage V.sub.g appears between the circuit board ground and the test system ground, as shown.
A voltage difference between the two grounds, i.e., or ground bounce, has extreme adverse effects as described hereafter. The output voltage of the driver 112 is maintained at a constant level with respect to the test system ground (assuming that the driver 112 is not switching). The board inputs of the circuit board 114 exhibit very high impedance, so very little current I.sub.d will flow through the fixture wiring having inductance L.sub.d. Thus, because the current I.sub.d is minimal, very little voltage V.sub.d is developed across the fixture wiring, pursuant to the aforementioned inductance equation. Moreover, the board input voltage will follow the driver output voltage, resulting in V.sub.g being impressed on the board input. When the ground bounce voltage is impressed on the board input, there is a risk of causing the input voltage to cross the logic threshold associated with the board input.
In the case of purely combinational logic circuit, the ground bounce predicament is not a severe risk, because a waiting period can be implemented to settle out the adverse effects. However, in the case of a sequential logic circuit for which this input is a clock or other state determining element, the state of the circuit is changed, and the test will fail no matter how slowly the test is advanced.